1. Field of the Invention
The present invention relates to circuits such as pulse density modulators, which represent a multi-bit digital input signal with a serial binary output comprising a corresponding sequence of fixed amplitude pulses. More particularly, the invention concerns such a system that uses novel circuitry to generate a binary output with the advantage that the pulses that are evenly spaced over time.
2. Description of the Related Art
Many circuits today have need for both digital and analog circuitry. Digital circuitry provides fast computation, parallel input/output, low power, and other benefits. Analog circuitry is nonetheless useful and sometimes essential in many applications, such as transmitting electromagnetic signals, controlling motors, applying power to loads, etc. To concurrently reap the benefits of both analog and digital circuitry, some circuits employ appropriate digital-to-analog converters and analog-to-digital converters. Today's market offers digital/analog converters with many different operating theories, speeds, and other specifications.
Known digital-to-analog chips provide significant advantages, primarily in the area of speed. Nonetheless, circuit designers still lament certain features of known digital-to-analog converter chips. For example, digital-to-analog converter chips consume a significant amount of power, which can be problematic for hand-held telephones and other applications that receive limited electrical power from a compact battery. Also, when incorporated into custom-designed integrated circuits, digital-to-analog converter chips typically occupy substantial size and thereby impinge upon the circuit designer's goal of producing produce the smallest possible overall circuit. Digital-to-analog circuits may also be prone to defects, since analog components are represented by narrow integrated circuit etchings with unforgiving tolerances. Finally, the inclusion of a digital-to-analog converter increases the cost and complexity of the manufacturing process, which then requires one manufacturing run to lay down digital components and a separate manufacturing run to lay down analog components.
One proposed solution to the limitations of known digital-to-analog converter chips is the pulse density modulation ("PDM") circuit. Many PDM circuits operate by receiving a multi-bit parallel digital input signal, and providing a corresponding serial binary output signal. The binary, digital output signal is then treated as an analog signal, which is averaged, smoothed, or otherwise filtered. The amplitude of this analog output signal is proportional to the multi-bit parallel digital input signal, and therefore constitutes an analog representation of the digital input signal.
One known PDM circuit operates by producing a single-pulse binary signal whose duty cycle is proportional to the multi-bit parallel input signal. This PDM is said to use pulse width modulation, or "PWM." The pulse width modulated output signal is fed to a low pass filter, creating an analog output signal that is roughly proportional to the original, multi-bit digital input signal. FIG. 1 shows a circuit 100 including an exemplary pulse width modulation system that utilizes a counter 100, comparator 102, and an analog low pass filter 104. The comparator 102 compares the output of the counter 100 to a digital input. When the input is larger or equal to the output of the counter, the comparator outputs a binary "one." Otherwise, the comparators output is a binary "zero." The low pass filter 104 processes the binary output, thus creating the final analog output signal. As explained below, one drawback of this approach is that the comparators binary "one" outputs are not evenly distributed over time.
FIGS. 2B-2I show serial binary outputs corresponding to inputs of zero through seven, respectively, from a pulse width modulation system utilizing the reference clock signal of FIG. 2A. When used in this manner, pulse width modulation has certain drawbacks. Chiefly, the approach of varying the duty cycle according to input signal has the effect of lumping binary output pulses together for larger multi-bit digital input signals.
FIG. 2B shows the serial binary output corresponding to a digital input of "zero." One multi-bit binary input is represented in one output period, such as the period 201. The output of FIG. 2B represents a single output pulse, and there is no problem with signal lumping. However, FIG. 2F shows the binary output corresponding to a multi-bit parallel digital input of "four." The output signal includes a contiguous high signal 200 (binary "1"), which actually represents five output pulses together. After the high signal 200, there is a contiguous low signal 202 (binary "0"). Due to the grouping high and low signals in this way, the analog output signal exhibits overshoots. This is because, upon applying the sequential binary output signal to an analog filter, the resulting analog signal overshoots in the realm of 200, and undershoots in the realm of 202, as shown by the superimposed analog signal 204.
A variation of the foregoing circuit outputs a binary "one" when the input is strictly larger than the output of the counter. Using strictly larger instead of "greater than or equal to" results in a difference of one pulse per period. For example, a digital input of zero in a system that uses a comparator that is strictly larger than the output of the counter will not output any "ones." However, a system that uses a comparator that is "greater or equal to" zero will have one digital "one" per period. This embodiment, like the previous example, has the drawback of unevenly distributing binary "ones" in the output signal.
As shown in FIG. 3, one solution to the foregoing problems of pulse width modulation was proposed in U.S. Pat. No. 5,337,338, Sutton et al., issued on Aug. 9, 1994. This approach uses a PDM 300 that is nearly identical to the circuit 100 of FIG. 1. The PDM 300 includes a counter 302, comparator 304, and analog low pass filter 306. However, unlike the circuit 100 (FIG. 1), the circuit 300 reverses the order of coupling 308. Namely, the mapping between most significant bits (MSBs) and least significant bits (LSBs) is swapped in the coupling between the counter 302 and the comparator 304.
FIGS. 4B-4I show serial binary outputs corresponding to inputs of zero through seven, respectively, utilizing the clock signal of FIG. 4A. A single period of the binary output is identified by 402. The purported advantage of this system is that, within a single period of the resulting serial binary output signal, like bits are not lumped together as much as the outputs of FIGS. 2B-2I. Nonetheless, as discovered by the present inventor, the output pulses are still not evenly spaced in FIGS. 4B-4I. For example, the representation of a "two" input has three "one" pulses in a period, and includes a non-symmetrical blank space 404. When filtered into an analog signal, these blank spots and lumps manifest themselves as signal overshoot. In some applications where accuracy is important, such overshoot may be unacceptable.
Thus, due to certain unsolved problems as shown above, known PDM circuits and digital-to-analog converters may not completely satisfactory for all applications.